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1. general description the lpc2131/32/34/36/38 microcontrollers are based on a 16/32-bit arm7tdmi-s cpu with real-time emulation and embedded trace support, that combine the microcontroller with 32 kb, 64 kb, 128 kb, 256 kb and 512 kb of embedded high-speed ?ash memory. a 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. for critical code size applications, the alternative 16-bit thumb mode reduces code by more than 30 % with minimal performance penalty. due to their tiny size and low power consumption, these microcontrollers are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. with a wide range of serial communications interfaces and on-chip sram options of 8 kb, 16 kb, and 32 kb, they are very well suited for communication gateways and protocol converters, soft modems, voice recognition and low-end imaging, providing both large buffer size and high processing power. various 32-bit timers, single or dual 10-bit 8-channel adc(s), 10-bit dac, pwm channels and 47 gpio lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems. 2. features 2.1 enhancements brought by lpc213x/01 devices n fast gpio ports enable port pin toggling up to 3.5 times faster than the original lpc213x. they also allow for a port pin to be read at any time regardless of its function. n dedicated result registers for adc(s) reduce interrupt overhead. n uart0/1 include fractional baud rate generator, auto-bauding capabilities and handshake ?ow-control fully implemented in hardware. n additional bod control enables further reduction of power consumption. 2.2 key features common for lpc213x and lpc213x/01 n 16/32-bit arm7tdmi-s microcontroller in a tiny lqfp64 or hvqfn package. n 8/16/32 kb of on-chip static ram and 32/64/128/256/512 kb of on-chip ?ash program memory. 128-bit wide interface/accelerator enables high-speed 60 mhz operation. n in-system programming/in-application programming (isp/iap) via on-chip bootloader software. single ?ash sector or full chip erase in 400 ms and programming of 256 b in 1 ms. n embeddedice rt and embedded trace interfaces offer real-time debugging with the on-chip realmonitor software and high-speed tracing of instruction execution. lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers; 32/64/128/256/512 kb isp/iap ?ash with 10-bit adc and dac rev. 04 16 october 2007 product data sheet
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 2 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers n one (lpc2131/32) or two (lpc2134/36/38) 8-channel 10-bit adcs provide a total of up to 16 analog inputs, with conversion times as low as 2.44 m s per channel. n single 10-bit dac provides variable analog output (lpc2132/34/36/38). n two 32-bit timers/external event counters (with four capture and four compare channels each), pwm unit (six outputs) and watchdog. n low power real-time clock with independent power and dedicated 32 khz clock input. n multiple serial interfaces including two uarts (16c550), two fast i 2 c-bus (400 kbit/s), spi and ssp with buffering and variable data length capabilities. n vectored interrupt controller with con?gurable priorities and vector addresses. n up to forty-seven 5 v tolerant general purpose i/o pins in tiny lqfp64 or hvqfn package. n up to nine edge or level sensitive external interrupt pins available. n 60 mhz maximum cpu clock available from programmable on-chip pll with settling time of 100 m s. n on-chip integrated oscillator operates with external crystal in range of 1 mhz to 30 mhz and with external oscillator up to 50 mhz. n power saving modes include idle and power-down. n individual enable/disable of peripheral functions as well as peripheral clock scaling down for additional power optimization. n processor wake-up from power-down mode via external interrupt or bod. n single power supply chip with por and bod circuits: u cpu operating voltage range of 3.0 v to 3.6 v (3.3 v 10 %) with 5 v tolerant i/o pads. 3. ordering information table 1. ordering information type number package name description version lpc2131fbd64 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 lpc2131fbd64/01 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 lpc2132fbd64 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 lpc2132fbd64/01 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 lpc2132fhn64 hvqfn64 plastic thermal enhanced very thin quad ?at package; no leads; 64 terminals; body 9 9 0.85 mm sot804-2 lpc2132fhn64/01 hvqfn64 plastic thermal enhanced very thin quad ?at package; no leads; 64 terminals; body 9 9 0.85 mm sot804-2 lpc2134fbd64 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 lpc2134fbd64/01 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 3 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 3.1 ordering options lpc2136fbd64 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 lpc2136fbd64/01 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 lpc2138fbd64 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 lpc2138fbd64/01 lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 lpc2138fhn64 hvqfn64 plastic thermal enhanced very thin quad ?at package; no leads; 64 terminals; body 9 9 0.85 mm sot804-2 lpc2138fhn64/01 hvqfn64 plastic thermal enhanced very thin quad ?at package; no leads; 64 terminals; body 9 9 0.85 mm sot804-2 table 1. ordering information continued type number package name description version table 2. ordering options type number flash memory ram adc dac enhanced uarts, adc, fast i/os, and bod temperature range lpc2131fbd64 32 kb 8 kb 1 - no - 40 c to +85 c lpc2131fbd64/01 32 kb 8 kb 1 - yes - 40 c to +85 c lpc2132fbd64 64 kb 16 kb 1 1 no - 40 c to +85 c lpc2132fbd64/01 64 kb 16 kb 1 1 yes - 40 c to +85 c lpc2132fhn64 64 kb 16 kb 1 1 no - 40 c to +85 c lpc2132fhn64/01 64 kb 16 kb 1 1 yes - 40 c to +85 c lpc2134fbd64 128 kb 16 kb 2 1 no - 40 c to +85 c lpc2134fbd64/01 128 kb 16 kb 2 1 yes - 40 c to +85 c lpc2136fbd64 256 kb 32 kb 2 1 no - 40 c to +85 c lpc2136fbd64/01 256 kb 32 kb 2 1 yes - 40 c to +85 c lpc2138fbd64 512 kb 32 kb 2 1 no - 40 c to +85 c lpc2138fbd64/01 512 kb 32 kb 2 1 yes - 40 c to +85 c lpc2138fhn64 512 kb 32 kb 2 1 no - 40 c to +85 c lpc2138fhn64/01 512 kb 32 kb 2 1 yes - 40 c to +85 c
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 4 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 4. block diagram (1) lpc2134/36/38 only. (2) lpc2132/34/36/38 only. (3) pins shared with gpio. fig 1. block diagram scl0,1 p0[31:0] p1[31:16] p0[31:0] p1[31:16] sda0,1 xtal2 xtal1 sck0,1 mosi0,1 miso0,1 eint[3:0] ad0[7:0] pwm[6:1] ssel0,1 txd0,1 rxd0,1 ahb bridge pll uart0/uart1 real time clock pwm0 arm7tdmi-s reset lpc2131, lpc2131/01 lpc2132, lpc2132/01 lpc2134, lpc2134/01 lpc2136, lpc2136/01 lpc2138, lpc2138/01 8 cap 8 mat ad1[7:0] (1) aout (2) dsr1 (1) ,cts1 (1) rts1 (1) , dtr1 (1) dcd1 (1) , ri1 (1) 002aab067 trst (3) tms (3) tck (3) tdi (3) tdo (3) trace signals fast general purpose i/o internal sram controller internal flash controller 8/16/32 kb sram 32/64/128/ 256/512 kb flash external interrupts capture/ compare timer 0/timer 1 a/d converters 0 and 1 (1) d/a converter (2) general purpose i/o system control watchdog timer rtcx2 rtcx1 spi and ssp serial interfaces i 2 c serial interfaces 0 and 1 apb (arm peripheral bus) ahb to apb bridge apb divider ahb decoder amba ahb (advanced high-performance bus) vectored interrupt controller system functions system clock emulation trace module test/debug interface arm7 local bus vbat
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 5 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 5. pinning information 5.1 pinning fig 2. lpc2131 lqfp64 pinning lpc2131 lpc2131/01 p0.21/pwm5/cap1.3 p1.20/tracesync p0.22/cap0.0/mat0.0 p0.17/cap1.2/sck1/mat1.2 rtcx1 p0.16/eint0/mat0.2/cap0.2 p1.19/tracepkt3 p0.15/eint2 rtcx2 p1.21/pipestat0 v ss v dd v dda v ss p1.18/tracepkt2 p0.14/eint1/sda1 p0.25/ad0.4 p1.22/pipestat1 p0.26/ad0.5 p0.13/mat1.1 p0.27/ad0.0/cap0.1/mat0.1 p0.12/mat1.0 p1.17/tracepkt1 p0.11/cap1.1/scl1 p0.28/ad0.1/cap0.2/mat0.2 p1.23/pipestat2 p0.29/ad0.2/cap0.3/mat0.3 p0.10/cap1.0 p0.30/ad0.3/eint3/cap0.0 p0.9/rxd1/pwm6/eint3 p1.16/tracepkt0 p0.8/txd1/pwm4 p0.31 p1.27/tdo v ss vref p0.0/txd0/pwm1 xtal1 p1.31/trst xtal2 p0.1/rxd0/pwm3/eint0 p1.28/tdi p0.2/scl0/cap0.0 v ssa v dd p0.23 p1.26/rtck reset v ss p1.29/tck p0.3/sda0/mat0.0/eint1 p0.20/mat1.3/ssel1/eint3 p0.4/sck0/cap0.1/ad0.6 p0.19/mat1.2/mosi1/cap1.2 p1.25/extin0 p0.18/cap1.3/miso1/mat1.3 p0.5/miso0/mat0.1/ad0.7 p1.30/tms p0.6/mosi0/cap0.2 v dd p0.7/ssel0/pwm2/eint2 v ss p1.24/traceclk vbat 002aab068 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 6 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers fig 3. lpc2132 lqfp64 pin con?guration lpc2132 lpc2132/01 p0.21/pwm5/cap1.3 p1.20/tracesync p0.22/cap0.0/mat0.0 p0.17/cap1.2/sck1/mat1.2 rtcx1 p0.16/eint0/mat0.2/cap0.2 p1.19/tracepkt3 p0.15/eint2 rtcx2 p1.21/pipestat0 v ss v dd v dda v ss p1.18/tracepkt2 p0.14/eint1/sda1 p0.25/ad0.4/aout p1.22/pipestat1 p0.26/ad0.5 p0.13/mat1.1 p0.27/ad0.0/cap0.1/mat0.1 p0.12/mat1.0 p1.17/tracepkt1 p0.11/cap1.1/scl1 p0.28/ad0.1/cap0.2/mat0.2 p1.23/pipestat2 p0.29/ad0.2/cap0.3/mat0.3 p0.10/cap1.0 p0.30/ad0.3/eint3/cap0.0 p0.9/rxd1/pwm6/eint3 p1.16/tracepkt0 p0.8/txd1/pwm4 p0.31 p1.27/tdo v ss vref p0.0/txd0/pwm1 xtal1 p1.31/trst xtal2 p0.1/rxd0/pwm3/eint0 p1.28/tdi p0.2/scl0/cap0.0 v ssa v dd p0.23 p1.26/rtck reset v ss p1.29/tck p0.3/sda0/mat0.0/eint1 p0.20/mat1.3/ssel1/eint3 p0.4/sck0/cap0.1/ad0.6 p0.19/mat1.2/mosi1/cap1.2 p1.25/extin0 p0.18/cap1.3/miso1/mat1.3 p0.5/miso0/mat0.1/ad0.7 p1.30/tms p0.6/mosi0/cap0.2 v dd p0.7/ssel0/pwm2/eint2 v ss p1.24/traceclk vbat 002aab406 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 7 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers fig 4. lpc2134/36/38 lqfp64 pin con?guration lpc2134, lpc2134/01 lpc2136, lpc2136/01 lpc2138, lpc2138/01 p0.21/pwm5/ad1.6/cap1.3 p1.20/tracesync p0.22/ad1.7/cap0.0/mat0.0 p0.17/cap1.2/sck1/mat1.2 rtcx1 p0.16/eint0/mat0.2/cap0.2 p1.19/tracepkt3 p0.15/ri1/eint2/ad1.5 rtcx2 p1.21/pipestat0 v ss v dd v dda v ss p1.18/tracepkt2 p0.14/dcd1/eint1/sda1 p0.25/ad0.4/aout p1.22/pipestat1 p0.26/ad0.5 p0.13/dtr1/mat1.1/ad1.4 p0.27/ad0.0/cap0.1/mat0.1 p0.12/dsr1/mat1.0/ad1.3 p1.17/tracepkt1 p0.11/cts1/cap1.1/scl1 p0.28/ad0.1/cap0.2/mat0.2 p1.23/pipestat2 p0.29/ad0.2/cap0.3/mat0.3 p0.10/rts1/cap1.0/ad1.2 p0.30/ad0.3/eint3/cap0.0 p0.9/rxd1/pwm6/eint3 p1.16/tracepkt0 p0.8/txd1/pwm4/ad1.1 p0.31 p1.27/tdo v ss vref p0.0/txd0/pwm1 xtal1 p1.31/trst xtal2 p0.1/rxd0/pwm3/eint0 p1.28/tdi p0.2/scl0/cap0.0 v ssa v dd p0.23 p1.26/rtck reset v ss p1.29/tck p0.3/sda0/mat0.0/eint1 p0.20/mat1.3/ssel1/eint3 p0.4/sck0/cap0.1/ad0.6 p0.19/mat1.2/mosi1/cap1.2 p1.25/extin0 p0.18/cap1.3/miso1/mat1.3 p0.5/miso0/mat0.1/ad0.7 p1.30/tms p0.6/mosi0/cap0.2/ad1.0 v dd p0.7/ssel0/pwm2/eint2 v ss p1.24/traceclk vbat 002aab407 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 8 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers ad1.7 to ad1.0 only available on lpc2134/36/38. fig 5. lpc2132/38 hvqfn64 pin con?guration 002aab943 lpc2132/2138 transparent top view 16 33 15 34 14 35 13 36 12 37 11 38 10 39 9 40 8 41 7 42 6 43 5 44 4 45 3 46 2 47 1 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 terminal 1 index area p0.21/pwm5/ad1.6/cap1.3 p0.22/ad1.7/cap0.0/mat0.0 rtcx1 p1.19/tracepkt3 rtcx2 v ss v dda p1.18/tracepkt2 p0.25/ad0.4/aout p0.26/ad0.5 p0.27/ad0.0/cap0.1/mat0.1 p1.17/tracepkt1 p0.28/ad0.1/cap0.2/mat0.2 p0.29/ad0.2/cap0.3/mat0.3 p0.30/ad0.3/eint3/cap0.0 p1.16/tracepkt0 p1.27/tdo vref xtal1 xtal2 p1.28/tdi v ssa p0.23 reset p1.29/tck p0.20/mat1.3/ssel1/eint3 p0.19/mat1.2/mosi1/cap1.2 p0.18/cap1.3/miso1/mat1.3 p1.30/tms v dd v ss vbat p1.20/tracesync p0.17/cap1.2/sck1/mat1.2 p0.16/eint0/mat0.2/cap0.2 p0.15/ri1/eint2/ad1.5 p1.21/pipestat0 v dd v ss p0.14/dcd1/eint1/sda1 p1.22/pipestat1 p0.13/dtr1/mat1.1/ad1.4 p0.12/dsr1/mat1.0/ad1.3 p0.11/cts1/cap1.1/scl1 p1.23/pipestat2 p0.10/rts1/cap1.0/ad1.2 p0.9/rxd1/pwm6/eint3 p0.8/txd1/pwm4/ad1.1 p0.31 v ss p0.0/txd0/pwm1 p1.31/trst p0.1/rxd0/pwm3/eint0 p0.2/scl0/cap0.0 v dd p1.26/rtck v ss p0.3/sda0/mat0.0/eint1 p0.4/sck0/cap0.1/ad0.6 p1.25/extin0 p0.5/miso0/mat0.1/ad0.7 p0.6/mosi0/cap0.2/ad1.0 p0.7/ssel0/pwm2/eint2 p1.24/traceclk
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 9 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 5.2 pin description table 3. pin description symbol pin type description p0.0 to p0.31 i/o port 0: port 0 is a 32-bit i/o port with individual direction controls for each bit. total of 31 pins of the port 0 can be used as a general purpose bidirectional digital i/os while p0.31 is output only pin. the operation of port 0 pins depends upon the pin function selected via the pin connect block. pin p0.24 is not available. p0.0/txd0/ pwm1 19 [1] o txd0 transmitter output for uart0. o pwm1 pulse width modulator output 1. p0.1/rxd0/ pwm3/eint0 21 [2] i rxd0 receiver input for uart0. o pwm3 pulse width modulator output 3. i eint0 external interrupt 0 input. p0.2/scl0/ cap0.0 22 [3] i/o scl0 i 2 c0 clock input/output. open drain output (for i 2 c-bus compliance). i cap0.0 capture input for timer 0, channel 0. p0.3/sda0/ mat0.0/eint1 26 [3] i/o sda0 i 2 c0 data input/output. open drain output (for i 2 c-bus compliance). o mat0.0 match output for timer 0, channel 0. i eint1 external interrupt 1 input. p0.4/sck0/ cap0.1/ad0.6 27 [4] i/o sck0 serial clock for spi0. spi clock output from master or input to slave. i cap0.1 capture input for timer 0, channel 1. i ad0.6 adc 0, input 6. this analog input is always connected to its pin. p0.5/miso0/ mat0.1/ad0.7 29 [4] i/o miso0 master in slave v dd = 3.6 v for spi0. data input to spi master or data output from spi slave. o mat0.1 match output for timer 0, channel 1. i ad0.7 adc 0, input 7. this analog input is always connected to its pin. p0.6/mosi0/ cap0.2/ad1.0 30 [4] i/o mosi0 master out slave in for spi0. data output from spi master or data input to spi slave. i cap0.2 capture input for timer 0, channel 2. i ad1.0 adc 1, input 0. this analog input is always connected to its pin. available in lpc2134/36/38 only. p0.7/ssel0/ pwm2/eint2 31 [2] i ssel0 slave select for spi0. selects the spi interface as a slave. o pwm2 pulse width modulator output 2. i eint2 external interrupt 2 input. p0.8/txd1/ pwm4/ad1.1 33 [4] o txd1 transmitter output for uart1. o pwm4 pulse width modulator output 4. i ad1.1 adc 1, input 1. this analog input is always connected to its pin. available in lpc2134/36/38 only. p0.9/rxd1/ pwm6/eint3 34 [2] i rxd1 receiver input for uart1. o pwm6 pulse width modulator output 6. i eint3 external interrupt 3 input. p0.10/rts1/ cap1.0/ad1.2 35 [4] o rts1 request to send output for uart1. available in lpc2134/36/38. i cap1.0 capture input for timer 1, channel 0. i ad1.2 adc 1, input 2. this analog input is always connected to its pin. available in lpc2134/36/38 only.
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 10 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers p0.11/cts1/ cap1.1/scl1 37 [3] i cts1 clear to send input for uart1. available in lpc2134/36/38. i cap1.1 capture input for timer 1, channel 1. i/o scl1 i 2 c1 clock input/output. open drain output (for i 2 c-bus compliance) p0.12/dsr1/ mat1.0/ad1.3 38 [4] i dsr1 data set ready input for uart1. available in lpc2134/36/38. o mat1.0 match output for timer 1, channel 0. i ad1.3 adc 1, input 3. this analog input is always connected to its pin. available in lpc2134/36/38 only. p0.13/dtr1/ mat1.1/ad1.4 39 [4] o dtr1 data terminal ready output for uart1. available in lpc2134/36/38. o mat1.1 match output for timer 1, channel 1. i ad1.4 adc 1, input 4. this analog input is always connected to its pin. available in lpc2134/36/38 only. p0.14/dcd1/ eint1/sda1 41 [3] i dcd1 data carrier detect input for uart1. available in lpc2134/36/38. i eint1 external interrupt 1 input. i/o sda1 i 2 c1 data input/output. open drain output (for i 2 c-bus compliance). p0.15/ri1/ eint2/ad1.5 45 [4] i ri1 ring indicator input for uart1. available in lpc2134/36/38. i eint2 external interrupt 2 input. i ad1.5 adc 1, input 5. this analog input is always connected to its pin. available in lpc2134/36/38 only. p0.16/eint0/ mat0.2/cap0.2 46 [2] i eint0 external interrupt 0 input. o mat0.2 match output for timer 0, channel 2. i cap0.2 capture input for timer 0, channel 2. p0.17/cap1.2/ sck1/mat1.2 47 [1] i cap1.2 capture input for timer 1, channel 2. i/o sck1 serial clock for ssp. clock output from master or input to slave. o mat1.2 match output for timer 1, channel 2. p0.18/cap1.3/ miso1/mat1.3 53 [1] i cap1.3 capture input for timer 1, channel 3. i/o miso1 master in slave out for ssp. data input to spi master or data output from ssp slave. o mat1.3 match output for timer 1, channel 3. p0.19/mat1.2/ mosi1/cap1.2 54 [1] o mat1.2 match output for timer 1, channel 2. i/o mosi1 master out slave in for ssp. data output from ssp master or data input to ssp slave. i cap1.2 capture input for timer 1, channel 2. p0.20/mat1.3/ ssel1/eint3 55 [2] o mat1.3 match output for timer 1, channel 3. i ssel1 slave select for ssp. selects the ssp interface as a slave. i eint3 external interrupt 3 input. p0.21/pwm5/ ad1.6/cap1.3 1 [4] o pwm5 pulse width modulator output 5. i ad1.6 adc 1, input 6. this analog input is always connected to its pin. available in lpc2134/36/38 only. i cap1.3 capture input for timer 1, channel 3. table 3. pin description continued symbol pin type description
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 11 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers p0.22/ad1.7/ cap0.0/mat0.0 2 [4] i ad1.7 adc 1, input 7. this analog input is always connected to its pin. available in lpc2134/36/38 only. i cap0.0 capture input for timer 0, channel 0. o mat0.0 match output for timer 0, channel 0. p0.23 58 [1] i/o general purpose digital input/output pin. p0.25/ad0.4/ aout 9 [5] i ad0.4 adc 0, input 4. this analog input is always connected to its pin. o aout dac output. not available in lpc2131. p0.26/ad0.5 10 [4] i ad0.5 adc 0, input 5. this analog input is always connected to its pin. p0.27/ad0.0/ cap0.1/mat0.1 11 [4] i ad0.0 adc 0, input 0. this analog input is always connected to its pin. i cap0.1 capture input for timer 0, channel 1. o mat0.1 match output for timer 0, channel 1. p0.28/ad0.1/ cap0.2/mat0.2 13 [4] i ad0.1 adc 0, input 1. this analog input is always connected to its pin. i cap0.2 capture input for timer 0, channel 2. o mat0.2 match output for timer 0, channel 2. p0.29/ad0.2/ cap0.3/mat0.3 14 [4] i ad0.2 adc 0, input 2. this analog input is always connected to its pin. i cap0.3 capture input for timer 0, channel 3. o mat0.3 match output for timer 0, channel 3. p0.30/ad0.3/ eint3/cap0.0 15 [4] i ad0.3 adc 0, input 3. this analog input is always connected to its pin. i eint3 external interrupt 3 input. i cap0.0 capture input for timer 0, channel 0. p0.31 17 [6] o general purpose digital output only pin. important: this pin must not be externally pulled low when reset pin is low or the jtag port will be disabled. p1.0 to p1.31 i/o port 1: port 1 is a 32-bit bidirectional i/o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block. pins 0 through 15 of port 1 are not available. p1.16/ tracepkt0 16 [6] o tracepkt0 trace packet, bit 0. standard i/o port with internal pull-up. p1.17/ tracepkt1 12 [6] o tracepkt1 trace packet, bit 1. standard i/o port with internal pull-up. p1.18/ tracepkt2 8 [6] o tracepkt2 trace packet, bit 2. standard i/o port with internal pull-up. p1.19/ tracepkt3 4 [6] o tracepkt3 trace packet, bit 3. standard i/o port with internal pull-up. p1.20/ tracesync 48 [6] o tracesync trace synchronization. standard i/o port with internal pull-up. low on tracesync while reset is low enables pins p1.25:16 to operate as trace port after reset. p1.21/ pipestat0 44 [6] o pipestat0 pipeline status, bit 0. standard i/o port with internal pull-up. p1.22/ pipestat1 40 [6] o pipestat1 pipeline status, bit 1. standard i/o port with internal pull-up. p1.23/ pipestat2 36 [6] o pipestat2 pipeline status, bit 2. standard i/o port with internal pull-up. table 3. pin description continued symbol pin type description
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 12 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers [1] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. [2] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. if con?gured for an input function, this pad utilizes built-in glitch ?lter that blocks pulses shorter than 3 ns. [3] open drain 5 v tolerant digital i/o i 2 c-bus 400 khz speci?cation compatible pad. it requires external pull-up to provide an output functionality. [4] 5 v tolerant pad providing digital i/o (with ttl levels and hysteresis and 10 ns slew rate control) and analog input function. if con?gured for an input function, this pad utilizes built-in glitch ?lter that blocks pulses shorter than 3 ns. when con?gured as an adc i nput, digital section of the pad is disabled. [5] 5 v tolerant pad providing digital i/o (with ttl levels and hysteresis and 10 ns slew rate control) and analog output function . when con?gured as the dac output, digital section of the pad is disabled. [6] 5 v tolerant pad with built-in pull-up resistor providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. the pull-up resistors value ranges from 60 k w to 300 k w . [7] 5 v tolerant pad providing digital input (with ttl levels and hysteresis) function only. [8] pad provides special analog functionality. p1.24/ traceclk 32 [6] o traceclk trace clock. standard i/o port with internal pull-up. p1.25/extin0 28 [6] i extin0 external trigger input. standard i/o with internal pull-up. p1.26/rtck 24 [6] i/o rtck returned test clock output. extra signal added to the jtag port. assists debugger synchronization when processor frequency varies. bidirectional pin with internal pull-up. low on rtck while reset is low enables pins p1.31:26 to operate as debug port after reset. p1.27/tdo 64 [6] o tdo test data out for jtag interface. p1.28/tdi 60 [6] i tdi test data in for jtag interface. p1.29/tck 56 [6] i tck test clock for jtag interface. p1.30/tms 52 [6] i tms test mode select for jtag interface. p1.31/ trst 20 [6] i trst test reset for jtag interface. reset 57 [7] i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. ttl with hysteresis, 5 v tolerant. xtal1 62 [8] i input to the oscillator circuit and internal clock generator circuits. xtal2 61 [8] o output from the oscillator ampli?er. rtcx1 3 [8] i input to the rtc oscillator circuit. rtcx2 5 [8] o output from the rtc oscillator circuit. v ss 6, 18, 25, 42, 50 i ground: 0 v reference. v ssa 59 i analog ground: 0 v reference. this should nominally be the same voltage as v ss , but should be isolated to minimize noise and error. v dd 23, 43, 51 i 3.3 v power supply: this is the power supply voltage for the core and i/o ports. v dda 7i analog 3.3 v power supply: this should be nominally the same voltage as v dd but should be isolated to minimize noise and error. this voltage is used to power the on-chip pll. vref 63 i adc reference: this should be nominally the same voltage as v dd but should be isolated to minimize noise and error. level on this pin is used as a reference for a/d and d/a convertor(s). vbat 49 i rtc power supply: 3.3 v on this pin supplies the power to the rtc. table 3. pin description continued symbol pin type description
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 13 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 6. functional description 6.1 architectural overview the arm7tdmi-s is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. the arm architecture is based on reduced instruction set computer (risc) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. this simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm7tdmi-s processor also employs a unique architectural strategy known as thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. the key idea behind thumb is that of a super-reduced instruction set. essentially, the arm7tdmi-s processor has two instruction sets: ? the standard 32-bit arm set. ? a 16-bit thumb set. the thumb sets 16-bit instruction length allows it to approach twice the density of standard arm code while retaining most of the arms performance advantage over a traditional 16-bit processor using 16-bit registers. this is possible because thumb code operates on the same 32-bit register set as arm code. thumb code is able to provide up to 65 % of the code size of arm, and 160 % of the performance of an equivalent arm processor connected to a 16-bit memory system. 6.2 on-chip ?ash program memory the lpc2131/32/34/36/38 incorporate a 32 kb, 64 kb, 128 kb, 256 kb and 512 kb ?ash memory system respectively. this memory may be used for both code and data storage. programming of the ?ash memory may be accomplished in several ways. it may be programmed in system via the serial port. the application program may also erase and/or program the ?ash while the application is running, allowing a great degree of ?exibility for data storage ?eld ?rmware upgrades, etc. when the lpc2131/32/34/36/38 on-chip bootloader is used, 32/64/128/256/500 kb of ?ash memory is available for user code. the lpc2131/32/34/36/38 ?ash memory provides a minimum of 100000 erase/write cycles and 20 years of data-retention. 6.3 on-chip static ram on-chip static ram may be used for code and/or data storage. the sram may be accessed as 8-bit, 16-bit, and 32-bit. the lpc2131, lpc2132/34, and lpc2136/38 provide 8 kb, 16 kb and 32 kb of static ram respectively.
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 14 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 6.4 memory map the lpc2131/32/34/36/38 memory map incorporates several distinct regions, as shown in figure 6 . in addition, the cpu interrupt vectors may be re-mapped to allow them to reside in either ?ash memory (the default) or on-chip static ram. this is described in section 6.18 system control . fig 6. lpc2131/32/34/36/38 memory map ahb peripherals vpb peripherals reserved address space reserved address space boot block (re-mapped from on-chip flash memory reserved address space total of 32 kb on-chip static ram (lpc2136/38) total of 16 kb on-chip static ram (lpc2132/34) total of 8 kb on-chip static ram (lpc2131) total of 512 kb on-chip non-volatile memory (lpc2138) total of 256 kb on-chip non-volatile memory (lpc2136) total of 128 kb on-chip non-volatile memory (lpc2134) 0xffff ffff 0xf000 0000 0xe000 0000 0xc000 0000 0x8000 0000 0x4000 4000 0x4000 3fff 0x4000 2000 0x4000 1fff 0x4001 8000 0x4000 7fff 0x4000 0000 0x0004 0000 0x0003 ffff 0x0002 0000 0x0001 ffff 0x0008 0000 0x0007 ffff 0x0001 0000 4.0 gb 3.75 gb 3.5 gb 3.0 gb 2.0 gb 1.0 gb total of 64 kb on-chip non-volatile memory (lpc2132) total of 32 kb on-chip non-volatile memory (lpc2131) 0x0000 ffff 0x0000 8000 0x0000 7fff 0x0000 0000 0.0 gb 002aab069
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 15 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 6.5 interrupt controller the vectored interrupt controller (vic) accepts all of the interrupt request inputs and categorizes them as fast interrupt request (fiq), vectored interrupt request (irq), and non-vectored irq as de?ned by programmable settings. the programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. fiq has the highest priority. if more than one request is assigned to fiq, the vic combines the requests to produce the fiq signal to the arm processor. the fastest possible fiq latency is achieved when only one request is classi?ed as fiq, because then the fiq service routine can simply start dealing with that device. but if more than one request is assigned to the fiq class, the fiq service routine can read a word from the vic that identi?es which fiq source(s) is (are) requesting an interrupt. vectored irqs have the middle priority. sixteen of the interrupt requests can be assigned to this category. any of the interrupt requests can be assigned to any of the 16 vectored irq slots, among which slot 0 has the highest priority and slot 15 has the lowest. non-vectored irqs have the lowest priority. the vic combines the requests from all the vectored and non-vectored irqs to produce the irq signal to the arm processor. the irq service routine can start by reading a register from the vic and jumping there. if any of the vectored irqs are requesting, the vic provides the address of the highest-priority requesting irqs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored irqs. the default routine can read another vic register to see what irqs are active. 6.5.1 interrupt sources t ab le 4 lists the interrupt sources for each peripheral function. each peripheral device has one interrupt line connected to the vectored interrupt controller, but may have several internal interrupt ?ags. individual interrupt ?ags may also represent more than one interrupt source. table 4. interrupt sources block flag(s) vic channel # wdt watchdog interrupt (wdint) 0 - reserved for software interrupts only 1 arm core embeddedice, dbgcommrx 2 arm core embeddedice, dbgcommtx 3 timer0 match 0 to 3 (mr0, mr1, mr2, mr3) capture 0 to 3 (cr0, cr1, cr2, cr3) 4 timer1 match 0 to 3 (mr0, mr1, mr2, mr3) capture 0 to 3 (cr0, cr1, cr2, cr3) 5 uart0 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) 6
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 16 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 6.6 pin connect block the pin connect block allows selected pins of the microcontroller to have more than one function. con?guration registers control the multiplexers to allow connection between the pin and the on chip peripherals. peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. activity of any enabled peripheral function that is not mapped to a related pin should be considered unde?ned. 6.7 general purpose parallel i/o and fast i/o device pins that are not connected to a speci?c peripheral function are controlled by the gpio registers. pins may be dynamically con?gured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back, as well as the current state of the port pins. 6.7.1 features ? direction control of individual bits. ? separate control of output set and clear. ? all i/o default to inputs after reset. uart1 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) modem status interrupt (msi) (available in lpc2134/36/38 only) 7 pwm0 match 0 to 6 (mr0, mr1, mr2, mr3, mr4, mr5, mr6) capture 0 to 3 (cr0, cr1, cr2, cr3) 8 i 2 c0 si (state change) 9 spi0 spif, modf 10 ssp tx fifo at least half empty (txris) rx fifo at least half full (rxris) receive timeout (rtris) receive overrun (rorris) 11 pll pll lock (plock) 12 rtc rtccif (counter increment), rtcalf (alarm) 13 system control external interrupt 0 (eint0) 14 external interrupt 1 (eint1) 15 external interrupt 2 (eint2) 16 external interrupt 3 (eint3) 17 ad0 adc 0 18 i2c1 si (state change) 19 bod brown out detect 20 ad1 adc 1 (available in lpc2134/36/38 only) 21 table 4. interrupt sources continued block flag(s) vic channel #
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 17 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 6.7.2 fast i/o features available in lpc213x/01 only ? fast i/o registers are located on the arm local bus for the fastest possible i/o timing. ? all gpio registers are byte addressable. ? entire port value can be written in one instruction. ? mask registers allow single instruction to set or clear any number of bits in one port. 6.8 10-bit adc the lpc2131/32 contain one and the lpc2134/36/38 contain two adcs. these converters are single 10-bit successive approximation adcs with eight multiplexed channels. 6.8.1 features ? measurement range of 0 v to 3.3 v. ? each converter capable of performing more than 400000 10-bit samples per second. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition on input pin or timer match signal. ? global start command for both converters (lpc2134/36/38 only). 6.8.2 adc features available in lpc213x/01 only ? every analog input has a dedicated result register to reduce interrupt overhead. ? every analog input can generate an interrupt once the conversion is completed. 6.9 10-bit dac this peripheral is available in the lpc2132/34/36/38 only. the dac enables the lpc2132/34/36/38 to generate variable analog output. 6.9.1 features ? 10-bit digital to analog converter. ? buffered output. ? power-down mode available. ? selectable speed versus power. 6.10 uarts the lpc2131/32/34/36/38 each contain two uarts. in addition to standard transmit and receive data lines, the lpc2134/36/38 uart1 also provides a full modem control handshake interface. 6.10.1 features ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 18 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers ? built-in baud rate generator. ? standard modem interface signals included on uart1. (lpc2134/36/38 only) ? the lpc2131/32/34/36/38 transmission fifo control enables implementation of software (xon/xoff) ?ow control on both uarts and hardware (cts/rts) ?ow control on the lpc2134/36/38 uart1 only. 6.10.2 uart features available in lpc213x/01 only ? fractional baud rate generator enables standard baud rates such as 115200 to be achieved with any crystal frequency above 2 mhz. ? auto-bauding. ? auto-cts/rts ?ow-control fully implemented in hardware (lpc2134/36/38 only). 6.11 i 2 c-bus serial i/o controller the lpc2131/32/34/36/38 each contain two i 2 c-bus controllers. the i 2 c-bus is bidirectional, for inter-ic control using only two wires: a serial clock line (scl), and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver or a transmitter with the capability to both receive and send information (such as memory)). transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. this i 2 c-bus implementation supports bit rates up to 400 kbit/s (fast i 2 c). 6.11.1 features ? standard i 2 c compliant bus interface. ? easy to con?gure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus may be used for test and diagnostic purposes. 6.12 spi serial i/o controller the lpc2131/32/34/36/38 each contain one spi controller. the spi is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master.
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 19 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 6.12.1 features ? compliant with serial peripheral interface (spi) speci?cation. ? synchronous, serial, full duplex, communication. ? combined spi master and slave. ? maximum data bit rate of one eighth of the input clock rate. 6.13 ssp serial i/o controller the lpc2131/32/34/36/38 each contain one serial synchronous port controller (ssp). the ssp controller is capable of operation on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. however, only a single master and a single slave can communicate on the bus during a given data transfer. the ssp supports full duplex transfers, with frames of 4 bits to 16 bits of data ?owing from the master to the slave and from the slave to the master. often only one of these data ?ows carries meaningful data. 6.13.1 features ? compatible with motorola spi, 4-wire ti ssi and national semiconductor microwire buses. ? synchronous serial communication. ? master or slave operation. ? 8-frame fifos for both transmit and receive. ? four bits to 16 bits per frame. 6.14 general purpose timers/external event counters the timer/counter is designed to count cycles of the peripheral clock (pclk) or an externally supplied clock, and optionally generate interrupts or perform other actions at speci?ed timer values, based on four match registers. it also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. multiple pins can be selected to perform a single capture or match function, providing an application with or and and, as well as broadcast functions among them. at any given time only one of peripherals capture inputs can be selected as an external event signal source, i.e., timers clock. the rate of external events that can be successfully counted is limited to pclk/2. in this con?guration, unused capture lines can be selected as regular timer capture inputs. 6.14.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? external event counter or timer operation. ? four 32-bit capture channels per timer/counter that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 32-bit match registers that allow: C continuous operation with optional interrupt generation on match.
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 20 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? four external outputs per timer/counter corresponding to match registers, with the following capabilities: C set low on match. C set high on match. C toggle on match. C do nothing on match. 6.15 watchdog timer the purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. when enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time. 6.15.1 features ? internally resets chip if not periodically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 32-bit timer with internal pre-scaler. ? selectable time period from (t cy(pclk) 256 4) to (t cy(pclk) 2 32 4) in multiples of t cy(pclk) 4. 6.16 real-time clock the real-time clock (rtc) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. the rtc has been designed to use little power, making it suitable for battery powered systems where the cpu is not running continuously (idle mode). 6.16.1 features ? measures the passage of time to maintain a calendar and clock. ? ultra-low power design to support battery powered systems. ? provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? can use either the rtc dedicated 32 khz oscillator input or clock derived from the external crystal/oscillator input at xtal1. programmable reference clock divider allows ?ne adjustment of the rtc. ? dedicated power supply pin can be connected to a battery or the main 3.3 v.
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 21 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 6.17 pulse width modulator the pwm is based on the standard timer block and inherits all of its features, although only the pwm function is pinned out on the lpc2131/32/34/36/38. the timer is designed to count cycles of the peripheral clock (pclk) and optionally generate interrupts or perform other actions when speci?ed timer values occur, based on seven match registers. the pwm function is also based on match register events. the ability to separately control rising and falling edge locations allows the pwm to be used for more applications. for instance, multi-phase motor control typically requires three non-overlapping pwm outputs with individual control of all three pulse widths and positions. two match registers can be used to provide a single edge controlled pwm output. one match register (mr0) controls the pwm cycle rate, by resetting the count upon match. the other match register controls the pwm edge position. additional single edge controlled pwm outputs require only one match register each, since the repetition rate is the same for all pwm outputs. multiple single edge controlled pwm outputs will all have a rising edge at the beginning of each pwm cycle, when an mr0 match occurs. three match registers can be used to provide a pwm output with both edges controlled. again, the mr0 match register controls the pwm cycle rate. the other match registers control the two pwm edge positions. additional double edge controlled pwm outputs require only two match registers each, since the repetition rate is the same for all pwm outputs. with double edge controlled pwm outputs, speci?c match registers control the rising and falling edge of the output. this allows both positive going pwm pulses (when the rising edge occurs prior to the falling edge), and negative going pwm pulses (when the falling edge occurs prior to the rising edge). 6.17.1 features ? seven match registers allow up to six single edge controlled or three double edge controlled pwm outputs, or a mix of both types. ? the match registers also allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? supports single edge controlled and/or double edge controlled pwm outputs. single edge controlled pwm outputs all go high at the beginning of each cycle unless the output is a constant low. double edge controlled pwm outputs can have either edge occur at any position within a cycle. this allows for both positive going and negative going pulses. ? pulse period and width can be any number of timer counts. this allows complete ?exibility in the trade-off between resolution and repetition rate. all pwm outputs will occur at the same repetition rate. ? double edge controlled pwm outputs can be programmed to be either positive going or negative going pulses.
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 22 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers ? match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. software must release new match values before they can become effective. ? may be used as a standard timer if the pwm mode is not enabled. ? a 32-bit timer/counter with a programmable 32-bit prescaler. 6.18 system control 6.18.1 crystal oscillator on-chip integrated oscillator operates with external crystal in range of 1 mhz to 30 mhz and with external oscillator up to 50 mhz. the oscillator output frequency is called f osc and the arm processor clock frequency is referred to as cclk for purposes of rate equations, etc. f osc and cclk are the same value unless the pll is running and connected. refer to section 6.18.2 pll for additional information. 6.18.2 pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up into the range of 10 mhz to 60 mhz with a current controlled oscillator (cco). the multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the cpu). the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is providing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. since the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle.the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must con?gure and activate the pll, wait for the pll to lock, then connect to the pll as a clock source. the pll settling time is 100 m s. 6.18.3 reset and wake-up timer reset has two sources on the lpc2131/32/34/36/38: the reset pin and watchdog reset. the reset pin is a schmitt trigger input pin with an additional glitch ?lter. assertion of chip reset by any source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a ?xed number of clocks have passed, and the on-chip ?ash controller has completed its initialization. when the internal reset is removed, the processor begins executing at address 0, which is the reset vector. at that point, all of the processor and peripheral registers have been initialized to predetermined values. the wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. this is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. since the oscillator and other functions are turned off during power-down mode, any wake-up of the processor from power-down mode makes use of the wake-up timer.
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 23 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers the wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. when power is applied to the chip, or some event caused the chip to exit power-down mode, some time is required for the oscillator to produce a signal of suf?cient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 6.18.4 brownout detector the lpc2131/32/34/36/38 include 2-stage monitoring of the voltage on the v dd pins. if this voltage falls below 2.9 v, the bod asserts an interrupt signal to the vectored interrupt controller. this signal can be enabled for interrupt; if not, software can monitor the signal by reading dedicated register. the second stage of low-voltage detection asserts reset to inactivate the lpc2131/32/34/36/38 when the voltage on the v dd pins falls below 2.6 v. this reset prevents alteration of the ?ash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. the bod circuit maintains this reset down below 1 v, at which point the por circuitry maintains the overall reset. both the 2.9 v and 2.6 v thresholds include some hysteresis. in normal operation, this hysteresis allows the 2.9 v detection to reliably interrupt, or a regularly-executed event loop to sense the condition. features available only in lpc213x/01 parts include ability to put the bod in power-down mode, turn it on or off and to control when the bod will reset the lpc213x/01 microcontroller. this can be used to further reduce power consumption when a low power mode (such as power down) is invoked. 6.18.5 code security this feature of the lpc2131/32/34/36/38 allow an application to control whether it can be debugged or protected from observation. if after reset on-chip bootloader detects a valid checksum in ?ash and reads 0x8765 4321 from address 0x1fc in ?ash, debugging will be disabled and thus the code in ?ash will be protected from observation. once debugging is disabled, it can be enabled only by performing a full chip erase using the isp. 6.18.6 external interrupt inputs the lpc2131/32/34/36/38 include up to nine edge or level sensitive external interrupt inputs as selectable pin functions. when the pins are combined, external events can be processed as four independent interrupt signals. the external interrupt inputs can optionally be used to wake up the processor from power-down mode. 6.18.7 memory mapping control the memory mapping control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. vectors may be mapped to the bottom of the on-chip ?ash memory, or to the on-chip static ram. this allows code running in different memory spaces to have control of the interrupts.
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 24 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 6.18.8 power control the lpc2131/32/34/36/38 support two reduced power modes: idle mode and power-down mode. in idle mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue operation during idle mode and may generate interrupts to cause the processor to resume execution. idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. in power-down mode, the oscillator is shut down and the chip receives no internal clocks. the processor state and registers, peripheral registers, and internal sram values are preserved throughout power-down mode and the logic levels of chip output pins remain static. the power-down mode can be terminated and normal operation resumed by either a reset or certain speci?c interrupts that are able to function without clocks. since all dynamic operation of the chip is suspended, power-down mode reduces chip power consumption to nearly zero. selecting an external 32 khz clock instead of the pclk as a clock-source for the on-chip rtc will enable the microcontroller to have the rtc active during power-down mode. power-down current is increased with rtc active. however, it is signi?cantly lower than in idle mode. a power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. 6.18.9 vpb bus the vpb divider determines the relationship between the processor clock (cclk) and the clock used by peripheral devices (pclk). the vpb divider serves two purposes. the ?rst is to provide peripherals with the desired pclk via vpb bus so that they can operate at the speed chosen for the arm processor. in order to achieve this, the vpb bus may be slowed down to 1 2 to 1 4 of the processor clock rate. because the vpb bus must work properly at power-up (and its timing cannot be altered if it does not work since the vpb divider control registers reside on the vpb bus), the default condition at reset is for the vpb bus to run at 1 4 of the processor clock rate. the second purpose of the vpb divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. because the vpb divider is connected to the pll output, the pll remains active (if it was running) during idle mode. 6.19 emulation and debugging the lpc2131/32/34/36/38 support emulation and debugging via a jtag serial port. a trace port allows tracing program execution. debugging and trace functions are multiplexed only with gpios on port 1. this means that all communication, timer and interface peripherals residing on port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself. 6.19.1 embeddedice standard arm embeddedice logic provides on-chip debug support. the debugging of the target system requires a host computer running the debugger software and an embeddedice protocol convertor. embeddedice protocol convertor converts the remote debug protocol commands to the jtag data needed to access the arm core.
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 25 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers the arm core has a debug communication channel function built-in. the debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program ?ow or even entering the debug state. the debug communication channel is accessed as a co-processor 14 by the program running on the arm7tdmi-s core. the debug communication channel allows the jtag port to be used for sending and receiving data without affecting the normal program ?ow. the debug communication channel data and control registers are mapped in to addresses in the embeddedice logic. 6.19.2 embedded trace since the lpc2131/32/34/36/38 have signi?cant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. the embedded trace macrocell provides real-time trace capability for deeply embedded processor cores. it outputs information about processor execution to the trace port. the etm is connected directly to the arm core and not to the main amba system bus. it compresses the trace information and exports it through a narrow trace port. an external trace port analyzer must capture the trace information under software debugger control. instruction trace (or pc trace) shows the ?ow of execution of the processor and provides a list of all the instructions that were executed. instruction trace is signi?cantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. trace information generation can be controlled by selecting the trigger resource. trigger resources include address comparators, counters and sequencers. since trace information is compressed the software debugger requires a static image of the code being executed. self-modifying code can not be traced because of this restriction. 6.19.3 realmonitor realmonitor is a con?gurable software module, developed by arm inc., which enables real time debug. it is a lightweight debug monitor that runs in the background while users debug their foreground application. it communicates with the host using the dcc, which is present in the embeddedice logic. the lpc2131/32/34/36/38 contain a speci?c con?guration of realmonitor software programmed into the on-chip ?ash memory.
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 26 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 7. limiting values [1] the following applies to the limiting values: a) this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] not to exceed 4.6 v. [4] the peak current is limited to 25 times the corresponding maximum current. [5] dependent on package type. [6] human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) - 0.5 +3.6 v v dda analog 3.3 v pad supply voltage - 0.5 +4.6 v v i(vbat) input voltage on pin vbat for the rtc - 0.5 +4.6 v v i(vref) input voltage on pin vref - 0.5 +4.6 v v ia analog input voltage on adc related pins - 0.5 +5.1 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd supply voltage is present [2] - 0.5 +6.0 v other i/o pins [2] - 0.5 v dd + 0.5 [3] v i dd supply current per supply pin - 100 [4] ma i ss ground current per ground pin - 100 [4] ma t stg storage temperature [5] - 40 +125 c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w v esd electrostatic discharge voltage human body model [6] all pins - 4000 +4000 v
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 27 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 8. static characteristics table 6. static characteristics t amb = - 40 c to +85 c for commercial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit v dd supply voltage (core and external rail) 3.0 3.3 3.6 v v dda analog 3.3 v pad supply voltage 2.5 3.3 3.6 v v i(vbat) input voltage on pin vbat 2.0 [2] 3.3 3.6 v v i(vref) input voltage on pin vref 3.0 3.3 3.6 v standard port pins, reset, rtck i il low-level input current v i = 0 v; no pull-up - - 3 m a i ih high-level input current v i =v dd ; no-pull-down - - 3 m a i oz off-state output current v o =0v; v o =v dd ; no pull-up/down --3 m a i latch i/o latch-up current - (0.5v dd ) < v i < (1.5v dd ); t j < 125 c - - 100 ma v i input voltage pin con?gured to provide a digital function [3] [4] [5] 0 - 5.5 v v o output voltage output active 0 - v dd v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage i oh = - 4 ma [6] v dd - 0.4 - - v v ol low-level output voltage i ol = - 4 ma [6] - - 0.4 v i oh high-level output current v oh =v dd - 0.4 v [6] - 4- - ma i ol low-level output current v ol = 0.4 v [6] 4--ma i ohs high-level short-circuit current v oh =0 v [7] -- - 45 ma i ols low-level short-circuit current v ol =v dda [7] - - 50 ma i pd pull-down current v i =5v [8] 10 50 150 m a i pu pull-up current v i =0 v [9] - 15 - 50 - 85 m a v dd < v i < 5 v [8] 000 m a i dd(act) active mode supply current v dd = 3.3 v; t amb =25 c; code while(1){} executed from ?ash, no active peripherals cclk = 10 mhz - 10 - ma cclk = 60 mhz - 40 - ma i dd(pd) power-down mode supply current v dd = 3.3 v; t amb =25 c - 60 - m a v dd = 3.3 v; t amb =85 c - 200 500 m a
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 28 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers [1] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. [2] the rtc typically fails when v i(vbat) drops below 1.6 v. [3] including voltage on outputs in 3-state mode. i batpd power-down mode battery supply current [10] rtc clock = 32 khz (from rtcx pins); t amb =25 c v dd = 3.0 v; v i(vbat) = 2.5 v - 14 - m a v dd = 3.0 v; v i(vbat) = 3.0 v - 16 - m a v dd = 3.3 v; v i(vbat) = 3.3 v - 18 - m a v dd = 3.6 v; v i(vbat) = 3.6 v - 20 - m a i batact active mode battery supply current [10] cclk = 60 mhz; pclk = 15 mhz; pclk enabled to rtck; rtc clock = 32 khz (from rtcx pins); t amb =25 c v dd = 3.0 v; v i(vbat) = 3.0 v - 78 - m a v dd = 3.3 v; v i(vbat) = 3.3 v - 80 - m a v dd = 3.6 v; v i(vbat) = 3.6 v - 82 - m a i batact(opt) optimized active mode battery supply current [10] [11] pclk disabled to rtck in the pconp register; rtc clock = 32 khz (from rtcx pins); t amb =25 c; v i(vbat) = 3.3 v cclk = 6 mhz - 21 - m a cclk = 25 mhz - 23 - m a cclk = 50 mhz - 27 - m a cclk = 60 mhz - 30 - m a i 2 c-bus pins v ih high-level input voltage [12] 0.7v dd --v v il low-level input voltage [12] - - 0.3v dd v v hys hysteresis voltage - 0.5v dd -v v ol low-level output voltage i ols = 3 ma [6] - - 0.4 v i li input leakage current v i =v dd [13] -24 m a v i =5v [13] -1022 m a oscillator pins v i(xtal1) input voltage on pin xtal1 0 - 1.8 v v o(xtal2) output voltage on pin xtal2 0 - 1.8 v v i(rtcx1) input voltage on pin rtcx1 0 - 1.8 v v o(rtcx2) output voltage on pin rtcx2 0 - 1.8 v table 6. static characteristics continued t amb = - 40 c to +85 c for commercial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 29 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers [4] v dd supply voltages must be present. [5] 3-state outputs go into 3-state mode when v dd is grounded. [6] accounts for 100 mv voltage drop in all supply lines. [7] only allowed for a short time period. [8] minimum condition for v i = 4.5 v, maximum condition for v i = 5.5 v. [9] applies to p1.16 to p1.25. [10] on pin vbat. [11] optimized for low battery consumption. [12] the input threshold voltage of i 2 c-bus pins meets the i 2 c-bus speci?cation, so an input voltage below 1.5 v will be recognized as a logic 0 while an input voltage above 3.0 v will be recognized as a logic 1. [13] to v ss . [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 7 . [3] the integral no-linearity (e l(adj) ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 7 . [4] the offset error (e o ) is the absolute difference between the straight line which ?ts the actual curve and the straight line which ?ts the ideal curve. see figure 7 . [5] the gain error (e g ) is the relative difference in percent between the straight line ?tting the actual transfer curve after removing offset error, and the straight line which ?ts the ideal transfer curve. see figure 7 . [6] the absolute voltage error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated a/d and the ideal transfer curve. see figure 7 . table 7. adc static characteristics v dda = 2.5 v to 3.6 v; t amb = - 40 c to +85 c, unless otherwise speci?ed; adc frequency 4.5 mhz. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v c ia analog input capacitance --1pf e d differential linearity error v ssa =0v, v dda = 3.3 v [1] [2] -- 1 lsb e l(adj) integral non-linearity v ssa =0v, v dda = 3.3 v [3] -- 2 lsb e o offset error v ssa =0v, v dda = 3.3 v [4] -- 3 lsb e g gain error v ssa =0v, v dda = 3.3 v [5] -- 0.5 % e t absolute error v ssa =0v, v dda = 3.3 v [6] -- 4 lsb
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 30 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 7. adc characteristics 002aac046 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda - v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 31 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 9. dynamic characteristics [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. [3] bus capacitance c b in pf, from 10 pf to 400 pf. fig 8. suggested adc interface - lpc2131/32/34/36/38 adx.y pin lpc2131/32/34/36/38 adx.y sample adx.y 20 k w 3 pf 5 pf r vsi v ss v ext 002aad452 table 8. dynamic characteristics t amb = - 40 c to +85 c for commercial applications, v dd over speci?ed ranges. [1] symbol parameter conditions min typ [2] max unit external clock f osc oscillator frequency 10 - 25 mhz t cy(clk) clock cycle time 40 - 100 ns t chcx clock high time t cy(clk) 0.4 - - ns t clcx clock low time t cy(clk) 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns port pins (except p0.2 and p0.3) t r(o) output rise time - 10 - ns t f(o) output fall time - 10 - ns i 2 c-bus pins (p0.2 and p0.3) t f(o) output fall time v ih to v il 20 + 0.1 c b [3] --ns
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 32 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 9.1 timing 9.2 lpc2138 power consumption measurements v dd = 1.8 v. fig 9. external clock timing t chcl t clcx t chcx t cy(clk) t clch 002aaa907 0.2v dd + 0.9 v 0.2v dd - 0.1 v v dd - 0.5 v 0.45 v test conditions: code executed from ?ash; all peripherals are enabled in pconp register; pclk = cclk/4. (1) v dd = 3.6 v at - 60 c (max) (2) v dd = 3.6 v at 140 c (3) v dd = 3.6 v at 25 c (4) v dd = 3.3 v at 25 c (typical) (5) v dd = 3.3 v at 95 c (typical) fig 10. i dd(act) measured at different frequencies (cclk) and temperatures 002aab404 20 10 30 40 0 frequency (mhz) 0 60 40 20 10 50 30 (1) (2) (3) (4) (5) i dd (ma)
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 33 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers test conditions: idle mode entered executing code from ?ash; all peripherals are enabled in pconp register; pclk = cclk/4. (1) v dd = 3.6 v at 140 c (max) (2) v dd = 3.6 v at - 60 c (3) v dd = 3.6 v at 25 c (4) v dd = 3.3 v at 25 c (typical) (5) v dd = 3.3 v at 95 c (typical) fig 11. i dd idle measured at different frequencies (cclk) and temperatures frequency (mhz) 0 60 (1) (2) (3) (4) (5) 40 20 10 50 30 002aab403 5 10 15 0 i dd (ma) test conditions: power-down mode entered executing code from ?ash; all peripherals are enabled in pconp register. (1) v dd = 3.6 v (2) v dd = 3.3 v (max) (3) v dd = 3.0 v (4) v dd = 3.3 v (typical) fig 12. i dd(pd) measured at different temperatures 002aab405 200 300 100 400 500 0 temp (c) - 60 140 100 20 60 - 20 i dd ( m a) (1) (2) (3) (4)
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 34 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 10. package outline fig 13. package outline sot314-2 (lqfp64) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 35 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers fig 14. package outline sot804-2 (hvqfn64) unit a max. a 1 d 1 a 4 bc e e h l e 1 y w v references outline version european projection issue date iec jedec jeita mm 1 0.05 0.00 0.80 0.65 0.30 0.18 0.5 7.5 e 2 7.5 0.2 7.25 6.95 d h 7.25 6.95 0.05 0.05 y 1 0.1 0.1 dimensions (mm are the original dimensions) 0.5 0.3 sot804-2 - - - mo-220 - - - 04-03-25 d 9.05 8.95 e 49 64 32 17 48 1 33 16 9.05 8.95 e 1 8.95 8.55 8.95 8.55 a detail x a 4 a 1 c d d 1 d h e 1 e hvqfn64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm sot804-2 0 5 10 mm scale e e b y y 1 c c b a a c c b v m w m e 1 e 2 e h l terminal 1 index area terminal 1 index area 1/2 e 1/2 e x
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 36 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 11. abbreviations table 9. acronym list acronym description adc analog-to-digital converter bod brownout detection cpu central processing unit dac digital-to-analog converter dcc debug communications channel fifo first in, first out gpio general purpose input/output jtag joint test action group pll phase-locked loop por power-on reset pwm pulse width modulator ram random access memory spi serial peripheral interface sram static random access memory ssp synchronous serial port uart universal asynchronous receiver/transmitter vpb vlsi peripheral bus
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 37 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 12. revision history table 10. revision history document id release date data sheet status change notice supersedes lpc2131_32_34_36_38_4 20071016 product data sheet - lpc2131_32_34_36_38_3 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? figure 1 : changed incorrect character font ? figure 5 : added ?gure note ? t ab le 3 : description for function ad1.3, pin 38, changed lpc2138 into lpc2134/36/38 ? figure 7 : added ? figure 9 : added ?gure note lpc2131_32_34_36_38_3 20060921 product data sheet - lpc2131_32_34_36_38_2 lpc2131_32_34_36_38_2 20050318 preliminary data sheet - lpc2131_2132_2138_1 lpc2131_2132_2138_1 20041118 preliminary data sheet - -
lpc2131_32_34_36_38_4 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 04 16 october 2007 38 of 39 nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers 13. legal information 13.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 13.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 13.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 13.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 14. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors lpc2131/32/34/36/38 single-chip 16/32-bit microcontrollers ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 16 october 2007 document identifier: lpc2131_32_34_36_38_4 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 15. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 enhancements brought by lpc213x/01 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 key features common for lpc213x and lpc213x/01 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 functional description . . . . . . . . . . . . . . . . . . 13 6.1 architectural overview. . . . . . . . . . . . . . . . . . . 13 6.2 on-chip ?ash program memory . . . . . . . . . . . 13 6.3 on-chip static ram. . . . . . . . . . . . . . . . . . . . . 13 6.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . 15 6.5.1 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 15 6.6 pin connect block . . . . . . . . . . . . . . . . . . . . . . 16 6.7 general purpose parallel i/o and fast i/o . . . 16 6.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.7.2 fast i/o features available in lpc213x/01 only 17 6.8 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.8.2 adc features available in lpc213x/01 only . . 17 6.9 10-bit dac . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.10 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.10.2 uart features available in lpc213x/01 only . 18 6.11 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 18 6.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.12 spi serial i/o controller. . . . . . . . . . . . . . . . . . 18 6.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.13 ssp serial i/o controller . . . . . . . . . . . . . . . . . 19 6.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.14 general purpose timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.15 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 20 6.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.16 real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 20 6.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.17 pulse width modulator . . . . . . . . . . . . . . . . . . 21 6.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.18 system control . . . . . . . . . . . . . . . . . . . . . . . . 22 6.18.1 crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 22 6.18.2 pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.18.3 reset and wake-up timer . . . . . . . . . . . . . . . . 22 6.18.4 brownout detector . . . . . . . . . . . . . . . . . . . . . 23 6.18.5 code security . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.18.6 external interrupt inputs . . . . . . . . . . . . . . . . . 23 6.18.7 memory mapping control. . . . . . . . . . . . . . . . 23 6.18.8 power control. . . . . . . . . . . . . . . . . . . . . . . . . 24 6.18.9 vpb bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.19 emulation and debugging. . . . . . . . . . . . . . . . 24 6.19.1 embeddedice . . . . . . . . . . . . . . . . . . . . . . . . 24 6.19.2 embedded trace. . . . . . . . . . . . . . . . . . . . . . . 25 6.19.3 realmonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26 8 static characteristics . . . . . . . . . . . . . . . . . . . 27 9 dynamic characteristics . . . . . . . . . . . . . . . . . 31 9.1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2 lpc2138 power consumption measurements 32 10 package outline . . . . . . . . . . . . . . . . . . . . . . . . 34 11 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 36 12 revision history . . . . . . . . . . . . . . . . . . . . . . . 37 13 legal information . . . . . . . . . . . . . . . . . . . . . . 38 13.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 38 13.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38 14 contact information . . . . . . . . . . . . . . . . . . . . 38 15 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
home a bout nxp news careers investors order/buy tech support contact my.nxp the lpc2131/32/34/36/38 microcontrollers are based on a 16/32-bit arm7tdmi-s cpu with real-time emulation and embedded trace su pport, that combine the microcontroller with 32 kb, 64 kb, 128 kb, 256 kb and 512 kb of embedded high-speed flash memory. a 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. for critical code size applications, the alternative 16-bit thumb mode reduces code by more than 30 pct wit h minimal performance penalty. due to their tiny size and low power consumption, these microcontrollers are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. with a wide range of serial communications interfaces and on-chip sram options of 8 kb, 16 kb, and 32 kb, they are very well su ited for communication gateways and protocol converters, soft modems, voice recognition and low-end imaging, providing both large buffer size and high processing power. various 32-bit timers, single or dual 10-bit 8-channel adc(s), 10-bit dac, pwm channels and 47 gpio lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers part icularly suitable for industrial control and medical systems. enhancements brought by lpc213x/01 devices fast gpio ports enable port pin toggling up to 3.5 times faster than the original lpc213x. they also allow for a port pin to be read at any time regardless of its function. dedicated result registers for adc(s) reduce interrupt overhead. uart0/1 include fractional baud rate generator, auto-bauding capabilities and handshake flow-control fully implemented in hardw are. additional bod control enables further reduction of power consumption. key features common for lpc213x and lpc213x/01 16/32-bit arm7tdmi-s microcontroller in a tiny lqfp64 or hvqfn package. 8/16/32 kb of on-chip static ram and 32/64/128/256/512 kb of on-chip flash program memory. 128-bit wide interface/accelerator e nables high-speed 60 mhz operation. in-system programming/in-application programming (isp/iap) via on-chip bootloader software. single flash sector or full chip er ase in 400 ms and programming of 256 b in 1 ms. embeddedice rt and embedded trace interfaces offer real-time debugging with the on-chip realmonitor software and high-speed tra cing of instruction execution. one (lpc2131/32) or two (lpc2134/36/38) 8-channel 10-bit adcs pr ovide a total of up to 16 analog inputs, with conversion times as low as 2.44 us per channel. single 10-bit dac provides variable analog output (lpc2132/34/36/38). two 32-bit timers/external event counters (with four capture and four compare channels each), pwm unit (six outputs) and watchd og. low power real-time clock with independent power and dedicated 32 khz clock input. multiple serial interfaces including two uarts (16c550), two fast i2c-bus (400 kbit/s), spi and ssp with buffering and variable data length capabilities. vectored interrupt controller with configurable priorities and vector addresses. up to forty-seven 5 v tolerant general purpose i/o pins in tiny lqfp64 or hvqfn package. up to nine edge or level sensitive external interrupt pins available. 60 mhz maximum cpu clock available from programmable on-chip pll with settling time of 100 us. on-chip integrated oscillator operates with external crystal in range of 1 mhz to 30 mhz and with external oscillator up to 50 mhz. power saving modes include idle and power-down. individual enable/disable of peripheral functions as well as peripheral clock scaling down for additional power optimization. processor wake-up from power-down mode via external interrupt or bod. single power supply chip with por and bod circuits: cpu operating voltage range of 3.0 v to 3.6 v (3.3 v +- 10 pct) with 5 v tolerant i/o pads. datasheet download datasheet download all documentation (product specification) v.4.0, 2007-10-16 pages, 699kb single-chip 16/32-bit microcontrollers; 32/64/128/256/512 kb isp/iap flash with 10-bit adc and dac all information hereunder is sub j ect to the subsequent disclaimers general description features and benefits applications quick reference parametrics/similar products block diagrams/pinning pricing/ordering/availability samples products/packages quality/reliability/chemical content design support print/email disclaimers general description hide back to top features and benefits hide back to top parametrics/similar products hide type number package f max (mhz) flash (kb) ram (kb) i/o pins uart i2c spi ssp adc timers pwm package reference code @ temperature range @ pll @ i/o supply voltage (v) @ cpu supply voltage (v) @ product description @ dac lpc2131fbd64 sot314-2 (lqfp64) 60.0 32.0 8.0 47.0 2.0 2.0 1.0 1.0 8.0 3.0 6.0 lqfp64 f y 3.3 3.3 32 kb isp/iap flash with 10-bit adc lpc2132fbd64 sot314-2 (lqfp64) 60.0 64.0 16.0 47.0 2.0 2.0 1.0 1.0 8.0 3.0 6.0 lqfp64 f y 3.3 3.3 64 kb isp/iap flash with 10-bit adc and dac 1.0 lpc2132fhn64 sot804-2 (hvqfn64) 60.0 64.0 16.0 47.0 2.0 2.0 1.0 1.0 8.0 3.0 6.0 hvqfn64 f y 3.3 3.3 64 kb isp/iap flash with 10-bit adc and dac 1.0 lpc2134fbd64 sot314-2 (lqfp64) 60.0 128.0 16.0 47.0 2.0 2.0 1.0 1.0 16.0 3.0 6.0 lqfp64 f y 3.3 3.3 128 kb isp/iap flash with 10-bit adc and dac 1.0 lpc2136fbd64 sot314-2 (lqfp64) 60.0 256.0 32.0 47.0 2.0 2.0 1.0 1.0 16.0 3.0 6.0 lqfp64 f y 3.3 3.3 256 kb isp/iap flash with 10-bit adc and dac 1.0 lpc2138fbd64 sot314-2 (lqfp64) 60.0 512.0 32.0 47.0 2.0 2.0 1.0 1.0 16.0 3.0 6.0 lqfp64 f y 3.3 3.3 512 kb isp/iap flash with 10-bit 1.0 lpc2131_32_34_36_38 preview product information selection guide applications looking for products microcontrollers arm7 (32-bit) lpc2131fbd64 select site: en g lish type search here search a dvanced search / selection guides page 1 of 5 single-chip 16/32- b it microcontrollers; 32/64/128/256/512 kb isp/iap flash with 10- b it ... 07-se p -2010 htt p ://www.nx p .com /
similar products lpc2131_32_34_36_38 links to the similar products page containing an overview of products that are similar in function or related to the type numb er(s) as listed on this page. the similar products page includes products from the same catalog tree(s), relevant selection guides and products from the same functional category. adc and dac lpc2138fhn64 sot804-2 (hvqfn64) 60.0 512.0 32.0 47.0 2.0 2.0 1.0 1.0 16.0 3.0 6.0 hvqfn64 f y 3.3 3.3 512 kb isp/iap flash with 10-bit adc and dac 1.0 back to top block diagrams hide back to top pricing/ordering/availability hide type number ordering code (12nc) orderable part number region distributor in stock order quantity inventory date buy online samples lpc2131fbd64/01 9352 817 71151 lpc2131fbd64/01,15 na mouser electronics 720 9/4/2010 buy online order samples na digi-key corporation 283 9/4/2010 buy online na mouser electronics 720 9/4/2010 buy online na future electronics 6,177 9/5/2010 buy online na arrow electronics 1,668 9/3/2010 buy online na wpg americas inc. 320 9/2/2010 buy online japan chip one stop yes 08/27/2010 buy online asia sac - taiwan yes 160160 09/01/2010 buy online asia wpi 1,600 160320 09/05/2010 buy online lpc2131fbd64/01 9352 817 71118 lpc2131fbd64/01,11 order samples lpc2132fbd64/01 9352 817 72118 lpc2132fbd64/01,11 order samples lpc2132fbd64/01 9352 817 72151 lpc2132fbd64/01,15 na mouser electronics 855 9/4/2010 buy online order samples na digi-key corporation 3,626 9/4/2010 buy online na mouser electronics 855 9/4/2010 buy online na future electronics 3,866 9/5/2010 buy online na avnet electronics marketing 2,165 9/3/2010 buy online na arrow electronics 4,723 9/3/2010 buy online na wpg americas inc. 320 9/2/2010 buy online na avnet electronics marketing 2,165 9/3/2010 buy online japan chip one stop yes 08/27/2010 buy online page 2 of 5 single-chip 16/32- b it microcontrollers; 32/64/128/256/512 kb isp/iap flash with 10- b it ... 07-se p -2010 htt p ://www.nx p .com /
the variants in the table below are discontinued. see the table discontinued information for more information. asia sac - taiwan yes 160160 09/01/2010 buy online asia wpi 10,000 160320 09/05/2010 buy online lpc2132fhn64/01 9352 817 73557 lpc2132fhn64/01,55 na digi-key corporation 1,300 9/4/2010 buy online order samples na arrow electronics 2,800 9/3/2010 buy online japan chip one stop yes 08/27/2010 buy online lpc2134fbd64/01 9352 817 74118 lpc2134fbd64/01,11 order samples lpc2134fbd64/01 9352 817 74151 lpc2134fbd64/01,15 na mouser electronics 445 9/4/2010 buy online order samples na digi-key corporation 5,137 9/4/2010 buy online na mouser electronics 445 9/4/2010 buy online na future electronics 5,965 9/5/2010 buy online na avnet electronics marketing 5 9/3/2010 buy online na arrow electronics 2,855 9/3/2010 buy online na wpg americas inc. 160 9/2/2010 buy online na avnet electronics marketing 5 9/3/2010 buy online japan chip one stop yes 08/27/2010 buy online lpc2136fbd64/01 9352 817 75151 lpc2136fbd64/01,15 na mouser electronics 150 9/4/2010 buy online order samples na digi-key corporation 3,017 9/4/2010 buy online na mouser electronics 150 9/4/2010 buy online na future electronics 17,214 9/5/2010 buy online na arrow electronics 7,149 9/3/2010 buy online na wpg americas inc. 320 9/2/2010 buy online japan chip one stop yes 08/27/2010 buy online asia wpi 1,600 160320 09/05/2010 buy online lpc2138fbd64/01 9352 817 76118 lpc2138fbd64/01,11 order samples lpc2138fbd64/01 9352 817 76151 lpc2138fbd64/01,15 na mouser electronics 1,210 9/4/2010 buy online order samples na digi-key corporation 6,875 9/4/2010 buy online na mouser electronics 1,210 9/4/2010 buy online na avnet electronics marketing 268 9/3/2010 buy online na arrow electronics 2,557 9/3/2010 buy online na wpg americas inc. 2,240 9/2/2010 buy online na avnet electronics marketing 268 9/3/2010 buy online japan chip one stop yes 08/27/2010 buy online asia wpi 1,600 160320 09/05/2010 buy online lpc2138fhn64/01 9352 817 79557 lpc2138fhn64/01,55 na mouser electronics 1,208 9/4/2010 buy online order samples na avnet electronics marketing 22,234 9/3/2010 buy online na digi-key corporation 5,628 9/4/2010 buy online na mouser electronics 1,208 9/4/2010 buy online na future electronics 1,245 9/5/2010 buy online na avnet electronics marketing 22,234 9/3/2010 buy online japan chip one stop yes 08/27/2010 buy online back to top products/packages hide type number orderable part number ordering code (12nc) product status package packing marking eccn lpc2131fbd64/01 lpc2131fbd64/01,15 9352 817 71151 volume production sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2131fbd64/01 lpc2131fbd64/01,11 9352 817 71118 volume production sot314-2 (lqfp64) reel pack, smd, 13" standard marking lpc2132fbd64/01 lpc2132fbd64/01,11 9352 817 72118 volume production sot314-2 (lqfp64) reel pack, smd, 13" standard marking lpc2132fbd64/01 lpc2132fbd64/01,15 9352 817 72151 volume production sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2132fhn64/01 lpc2132fhn64/01,55 9352 817 73557 volume production sot804-2 (hvqfn64) tray dry pack, bakeable, multiple standard marking lpc2134fbd64/01 lpc2134fbd64/01,11 9352 817 74118 volume production sot314-2 (lqfp64) reel pack, smd, 13" standard marking lpc2134fbd64/01 lpc2134fbd64/01,15 9352 817 74151 volume production sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2136fbd64/01 lpc2136fbd64/01,15 9352 817 75151 volume production sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2138fbd64/01 lpc2138fbd64/01,11 9352 817 76118 volume production sot314-2 (lqfp64) reel pack, smd, 13" standard marking lpc2138fbd64/01 lpc2138fbd64/01,15 9352 817 76151 volume production sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2138fhn64/01 lpc2138fhn64/01,55 9352 817 79557 volume production sot804-2 (hvqfn64) tray dry pack, bakeable, multiple standard marking type number orderable part number ordering code (12nc) product status package packing marking eccn lpc2131fbd64/cp3259 lpc2131fbd64/cp325 9352 881 15151 discontinued replacement product sot314-2 (lqfp64) tray pack, bakeable, single standard marking withdrawn sot314-2 page 3 of 5 single-chip 16/32- b it microcontrollers; 32/64/128/256/512 kb isp/iap flash with 10- b it ... 07-se p -2010 htt p ://www.nx p .com /
the variants in the table below are discontinued. see the table discontinued information for more information. quality and reliability disclaimer lpc2131fbd64 lpc2131fbd64,151 9352 784 93151 replacement product (lqfp64) tray pack, bakeable, single standard marking lpc2132fbd64/cp3252 lpc2132fbd64/cp325 9352 852 55151 withdrawn replacement product sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2132fbd64 lpc2132fbd64,151 9352 777 94151 withdrawn replacement product sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2132fbd64/01/s lpc2132fbd64/01/s, 9352 894 13151 discontinued replacement product sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2132fhn64 lpc2132fhn64,557 9352 798 83557 withdrawn replacement product sot804-2 (hvqfn64) tray dry pack, bakeable, multiple standard marking lpc2134fbd64/01/s lpc2134fbd64/01/s, 9352 893 91151 withdrawn replacement product sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2134fbd64 lpc2134fbd64,151 9352 785 32151 withdrawn replacement product sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2136fbd64/00 lpc2136fbd64/00,15 9352 826 85151 withdrawn replacement product sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2136fbd64 lpc2136fbd64,151 9352 785 33151 withdrawn replacement product sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2136fbd64/01 - 9352 817 75118 withdrawn replacement product sot314-2 (lqfp64) reel pack, smd, 13" standard marking lpc2138fbd64 lpc2138fbd64,151 9352 777 95151 withdrawn replacement product sot314-2 (lqfp64) tray pack, bakeable, single standard marking lpc2138fhn64 lpc2138fhn64,557 9352 798 21557 withdrawn replacement product sot804-2 (hvqfn64) tray dry pack, bakeable, multiple standard marking back to top quality/reliability/chemical content hide type number orderable part number chemical content rohs leadfree conversion date rhf ifr (fit) mtbf (hours) msl lpc2131fbd64/01 lpc2131fbd64/01,15 lpc2131fbd64/01 always pb-free 2,84 2,58e+08 1 lpc2131fbd64/01 lpc2131fbd64/01,11 lpc2131fbd64/01 always pb-free 2,84 2,58e+08 1 lpc2132fbd64/01 lpc2132fbd64/01,11 lpc2132fbd64/01 always pb-free 2,84 2,58e+08 1 lpc2132fbd64/01 lpc2132fbd64/01,15 lpc2132fbd64/01 always pb-free 2,84 2,58e+08 1 lpc2132fhn64/01 lpc2132fhn64/01,55 lpc2132fhn64/01 always pb-free 2,84 2,58e+08 3 lpc2134fbd64/01 lpc2134fbd64/01,11 lpc2134fbd64/01 always pb-free 2,84 2,58e+08 1 lpc2134fbd64/01 lpc2134fbd64/01,15 lpc2134fbd64/01 always pb-free 2,84 2,58e+08 1 lpc2136fbd64/01 lpc2136fbd64/01,15 lpc2136fbd64/01 always pb-free 2,84 2,58e+08 1 lpc2138fbd64/01 lpc2138fbd64/01,11 lpc2138fbd64/01 always pb-free 2,84 2,58e+08 1 lpc2138fbd64/01 lpc2138fbd64/01,15 lpc2138fbd64/01 always pb-free 2,84 2,58e+08 1 lpc2138fhn64/01 lpc2138fhn64/01,55 lpc2138fhn64/01 always pb-free 2,84 2,58e+08 3 type number orderable part number chemical content rohs leadfree conversion date rhf ifr (fit) mtbf (hours) msl lpc2131fbd64/cp3259 lpc2131fbd64/cp325 lpc2131fbd64/cp3259 always pb-free 2,84 2,58e+08 1 lpc2131fbd64 lpc2131fbd64,151 always pb-free 2,84 2,58e+08 1 lpc2132fbd64/cp3252 lpc2132fbd64/cp325 always pb-free 2,84 2,58e+08 1 lpc2132fbd64 lpc2132fbd64,151 always pb-free 2,84 2,58e+08 1 lpc2132fbd64/01/s lpc2132fbd64/01/s, lpc2132fbd64/01/s always pb-free 2,84 2,58e+08 1 lpc2132fhn64 lpc2132fhn64,557 always pb-free 2,84 2,58e+08 3 lpc2134fbd64/01/s lpc2134fbd64/01/s, always pb-free 2,84 2,58e+08 1 lpc2134fbd64 lpc2134fbd64,151 always pb-free 2,84 2,58e+08 1 lpc2136fbd64/00 lpc2136fbd64/00,15 always pb-free 1 lpc2136fbd64 lpc2136fbd64,151 always pb-free 2,84 2,58e+08 1 lpc2136fbd64/01 - lpc2136fbd64/01 always pb-free 2,84 2,58e+08 1 lpc2138fbd64 lpc2138fbd64,151 always pb-free 2,84 2,58e+08 1 lpc2138fhn64 lpc2138fhn64,557 always pb-free 2,84 2,58e+08 3 back to top discontinued information hide type number ordering code (12nc) last-time buy date last-time delivery date replacement product dn notice status comments lpc2131fbd64/cp3259 935288115151 30-jan-10 31-mei-10 lpc2131fbd64/01 dn 65 customer specific product limited availability (check with your usual sales contact) limited availability. lpc2131fbd64 935278493151 30-sep-08 31-dec-08 lpc2131fbd64/01 dn 60 sole source product standard availability standard end of life. see replacement. lpc2132fbd64/cp3252 935285255151 31-mar-09 30-jun-09 lpc2132fbd64/01 dn 61 sole source product standard availability standard end of life. lpc2132fbd64 935277794151 30-sep-08 31-dec-08 lpc2132fbd64/01 dn 60 sole source product standard availability standard end of life. see replacement. lpc2132fbd64/01/s 935289413151 30-jan-10 31-mei-10 lpc2132fbd64/01 dn 65 customer specific product limited availability (check with your usual sales contact) limited availability. lpc2132fhn64 935279883557 30-sep-08 31-dec-08 lpc2132fhn64/01 dn 60 sole source product standard availability standard end of life. see replacement. page 4 of 5 single-chip 16/32- b it microcontrollers; 32/64/128/256/512 kb isp/iap flash with 10- b it ... 07-se p -2010 htt p ://www.nx p .com /
application note using iap for lpc2000 arm devices (v.2.0, 2004-10-25) nichelite for lpc implementation notes (v.2.0, 2009-07-16) migrating to the lpc1700 series (v.1.0, 2009-10-06) lpc2000 secondary bootloader for code update using iap (v.1.0, 2009-05-26) philips arm lpc microcontroller family (v.2.0, 2004-10-25) using the philips lpc2000 flash utility with the keil mcb2100 and iar lpc210x kickstart evaluation boards (v.4.0, 2010-02-16) philips lpc2xxx family phase lock loop (v.1.0, 2004-11-01) entering isp mode from user code (v.3.0, 2006-09-06) nesting of interrupts in the lpc2000 (v.1.0, 2005-06-06) connecting ethernet interface with lpc2000 (v.1.0, 2007-02-09) initialization code/hints for the lpc2000 family (v.1.0, 2005-11-01) uc/os-ii time management in lpc2000 (v.2.0, 2007-07-18) handling of spurious interrupts in the lpc2000 (v.1.0, 2006-01-04) power management for lpc2138 (v.1.0, 2006-01-06) migrating to the lpc2300/2400 family (v.1.0, 2007-02-05) realizing an mp3 player with the lpc2148, using libmad and efsl (v.1.0, 2007-04-23) interfacing nxp bridge ic with nxp arm microcontroller (v.1.0, 2007-02-26) brushless dc motor control using the lpc2141 (v.1.0, 2007-10-18) full-duplex software uart for lpc2000 (v.1.0, 2008-01-18) lpc2138 extreme power down application note (v.1.0, 2006-12-15) using the rtc efficiently in the lpc213x (v.1.0, 2005-06-06) brochure looking for more 32-bit mcu options? start here. (v.1.0, 2009-04-01) create smarter, more efficient white goods; an industry-leading portfolio of cost-effective, power-saving solutions for major h ome appliances (v.1.0, 2008-06-01) errata sheet errata sheet lpc2131/01 (v.1.3, 2009-02-09) errata sheet lpc2131 (v.1.2, 2008-06-07) errata sheet lpc2132/01 (v.1.3, 2009-02-09) errata sheet lpc2132 (v.1.9, 2008-06-07) errata sheet lpc2134/01 (v.1.3, 2009-02-09) errata sheet lpc2134 (v.1.9, 2008-06-07) errata sheet lpc2136/01 (v.1.3, 2009-02-09) errata sheet lpc2136 (v.1.9, 2008-06-07) errata sheet lpc2138/01 (v.1.3, 2009-02-09) errata sheet lpc2138 (v.1.9, 2008-06-07) line card the choice for embedded technologies (v.1.0, 2009-04-01) development tools for arm-based mcus; select from the best in support (v.1.0, 2009-06-01) other type an10835 - lpc2000 series secondary bootloader source code (v.1.0, 2009-05-27) lfpak power mosfets and lpc microcontrollers (v.1.0, 2006-11-01) lpc2xxx uart transmitter code example (v.1.0, 2005-09-19) lpc2xxx spi master code example (v.1.0, 2006-01-20) lpc2000 eint dual edge interrupts (v.1.0, 2006-02-22) lpc2000 adc code example (v.1.0, 2006-03-27) lpc2000 i2c slave code example (v.1.0, 2006-04-21) lpc2000 spi slave code example (v.1.0, 2006-06-16) 60-mhz, 32-bit microcontroller with arm7tdmi-s(tm) core lpc213x (v.1.0, 2007-01-01) user manual volume 1: lpc213x user manual (v.1.0, 2005-06-24) support links inside the lpc2000... tips and tricks lpc2000 eda files (ibis, bsdl, orcad, pads, etc.) lpczone training video - ntru encryption overview training sample code bundle for lpc213x/lpc214x peripherals using keil's mdk-arm email this product information print this product information general product disclaimer quality and reliability disclaimer lpc2134fbd64/01/s 935289391151 31-dec-09 31-dec-09 lpc2134fbd64/01 dn 65 customer specific product non-availability. no last time buy possible type number fully withdrawn non-manufacturable. lpc2134fbd64 935278532151 30-sep-08 31-dec-08 lpc2134fbd64/01 dn 60 sole source product standard availability standard end of life. see replacement. lpc2136fbd64/00 935282685151 30-sep-07 31-dec-07 lpc2136fbd64/01 dn 58 sole source product standard availability standard end of life. see replacement. lpc2136fbd64 935278533151 30-sep-08 31-dec-08 lpc2136fbd64/01 dn 60 sole source product standard availability standard end of life. see replacement. lpc2136fbd64/01 935281775118 dn lpc2138fbd64 935277795151 30-sep-08 31-dec-08 lpc2138fbd64/01 dn 60 sole source product standard availability standard end of life. see replacement. lpc2138fhn64 935279821557 30-sep-08 31-dec-08 lpc2138fhn64/01 dn 60 sole source product standard availability standard end of life. see replacement. back to top design support hide back to top print/email hide back to top disclaimers hide nxp | privacy policy | terms of use | sitemap | mobile app | switch to classic mode ?2006-2010 nxp semiconductors. all rights reserved. page 5 of 5 single-chip 16/32- b it microcontrollers; 32/64/128/256/512 kb isp/iap flash with 10- b it ... 07-se p -2010 htt p ://www.nx p .com /

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